The most popular forms of memory modules are commonly known as DDR4 and DDR3, DDR2, and DDR. SDRAM is a generic term for much older pre-DDR RAM technology, with most systems that use this type of RAM since retired.
In just about any notebook, desktop, server or Mac, one of these types of modules will be used as the main system memory, and are generically referred to as 'DIMMs' (Dual Inline Memory Modules).
Various types of computer memory
SDR SDRAM
168-pin SDR SDRAM DIMM
144-pin SDR SDRAM SO-DIMM
Single data rate (SDR) SDRAM is an older type of memory, commonly used in computers prior to 2001. SDR SDRAM memory is often referred to simply as 'SDRAM'.
Typical clock frequencies are 100Mhz and 133MHz. SDR SDRAM modules are usually made in a 168-pin form factor for desktops, and a 144-pin form factor for notebook applications.
DDR SDRAM
Double data rate (DDR) SDRAM hit the mainstream computer market around 2002 and is a straightforward evolution from SDR SDRAM.
The most significant difference between DDR and SDR is that DDR uses 'double pumping' (transferring data on both the rising and falling edges of the clock signal) to allow data transfer rates that are double that of the earlier SDR SDRAM technology.
DDR SDRAM modules for desktop computers have 184 pins (as opposed to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM for notebook computers, SO-DIMMs, have 200 pins, which is the same number of pins as DDR2 SO-DIMMs.
184-pin DDR DIMM
200-pin DDR SO-DIMM
With the introduction of competing DDR SDRAM memory, the DDR standards group JEDEC turned against the standard clock speed naming schemes such as PC100 and PC133 used for the older SDR SDRAM modules, and instead named their parts by the amount of peak bandwidth they could utilize.
This results in a DDR module running at 200Mhz being referred to as DDR-400, or PC-3200, representing its peak bandwidth capability of 3200MB/s. The JEDEC standards for DDR memory are listed below:
| Standard name | Memory clock (MHz) |
Cycle time (ns) |
I/O bus clock (MHz) |
Data rate (MT/s) |
VDDQ (V) |
Module name | Peak transfer rate (MB/s) |
Timings (CL-tRCD-tRP) |
|---|---|---|---|---|---|---|---|---|
| DDR-200 | 100 | 10 | 100 | 200 | 2.5±0.2 | PC-1600 | 1600 | |
| DDR-266 | 133⅓ | 7.5 | 133⅓ | 266⅔ | 2.5±0.2 | PC-2100 | 2133⅓ | |
| DDR-333 | 166⅔ | 6 | 166⅔ | 333⅓ | 2.5±0.2 | PC-2700 | 2666⅔ | |
| DDR-400A DDR-400B DDR-400C |
200 | 5 | 200 | 400 | 2.6±0.1 | PC-3200 | 3200 | 2.5-3-3 3-3-3 3-4-4 |
DDR2 SDRAM
DDR2, the successor to DDR, was introduced in the second quarter of 2003. DDR2 supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM. DDR2 is neither forward nor backward compatible with either DDR or DDR3.
Frequently, DDR2 based systems can use memory installed in pairs to run in "dual channel mode" to increase memory bus throughput even further.
For use in desktop computers and servers, DDR2 SDRAM is supplied in DIMMs with 240 pins and a single locating notch. Laptop DDR2 SO-DIMMs have 200 pins, like the previous generation DDR SO-DIMMS.
240-pin DDR2 DIMM
200-pin DDR2 SO-DIMM
DDR2 requires less power primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage (1.8 V compared to DDR's 2.5 V).
Like DDR, DDR2 DIMMs are identified by their peak transfer capacity (often called bandwidth). The JEDEC standards for DDR2 memory are listed below:
| Standard name
|
Memory clock
(MHz) |
Cycle time
(ns) |
I/O bus clock
(MHz) |
Data rate
(MT/s) |
Module name
|
Peak transfer rate
(MB/s) |
(CL-tRCD-tRP) |
(ns) |
|---|---|---|---|---|---|---|---|---|
| DDR2-400B DDR2-400C |
100 | 10 | 200 | 400 | PC2-3200 | 3200 | 3-3-3 4-4-4 |
15 20 |
| DDR2-533B DDR2-533C |
133⅓ | 7½ | 266⅔ | 533⅓ | PC2-4200* | 4266⅔ | 3-3-3 4-4-4 |
11¼ 15 |
| DDR2-667C DDR2-667D |
166⅔ | 6 | 333⅓ | 666⅔ | PC2-5300* | 5333⅓ | 4-4-4 5-5-5 |
12 15 |
| DDR2-800C DDR2-800D DDR2-800E |
200 | 5 | 400 | 800 | PC2-6400 | 6400 | 4-4-4 5-5-5 6-6-6 |
10 12½ 15 |
| DDR2-1066E DDR2-1066F |
266⅔ | 3¾ | 533⅓ | 1066⅔ | PC2-8500* | 8533⅓ | 6-6-6 7-7-7 |
11¼ 13⅛ |
In addition to bandwidth and capacity variants, DDR2 modules can optionally implement:
- ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC2-4200 ECC or PC2-4200E is a PC2-4200 module with ECC.
- Be "registered" ("buffered"), which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, e.g. PC2-4200R. Typically modules with this designation are actually ECC Registered, but the 'E' of 'ECC' is not always shown. Whereas non-registered (a.k.a. unbuffered RAM) may be identified by an additional U in the designation. e.g. PC2-4200U.
- Be fully buffered modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.
DDR3 SDRAM
Although being superceded by DDR4 in many newer systems now, DDR3 is still very popular as of 2019, and began to appear in systems in late 2007. Compared to DDR2 memory, DDR3 memory uses 30% less power with a typical supply voltage of just 1.5V. DDR3 can also transfer data at rates up to 12.8 GB per second.
DDR3 DIMMs have 240 pins and are electrically incompatible with DDR2. The two are prevented from being accidentally interchanged by different key notch positions on the DIMMs. DDR3 SO-DIMMs have 204 pins.
240-pin DDR3 DIMM
204-pin DDR3 SO-DIMM
Lower voltage DDR3 modules, known as DDR3L and DDR3U, are also becoming increasingly popular. JEDEC introduced two low-voltage standards. The DDR3L standard is 1.35V and has the label ’’PC3L’’ for its modules. Examples include DDR3L‐800, DDR3L‐1066, DDR3L‐1333, and DDR3L‐1600. The DDR3U standard is 1.25V and has the label ’’PC3U’’ for its modules.
Like DDR and DDR2 before them, DDR3 DIMMs are identified by their peak transfer capacity (often called bandwidth). The JEDEC standards for DDR3 memory are listed below:
| Standard name
|
Memory clock
(MHz) |
Cycle time
(ns) |
I/O bus clock
(MHz) |
Data rate
(MT/s) |
Module name
|
Peak transfer rate
(MB/s) |
Timings
(CL-tRCD-tRP) |
CAS latency
(ns) |
|---|---|---|---|---|---|---|---|---|
| DDR3-800D DDR3-800E |
100 | 10 | 400 | 800 | PC3-6400 | 6400 | 5-5-5 6-6-6 |
12 15 |
| DDR3-1066E DDR3-1066F DDR3-1066G |
133⅓ | 7 | 533⅓ | 1066⅔ | PC3-8500 | 8533⅓ | 6-6-6 7-7-7 8-8-8 |
11 13 15 |
| DDR3-1333F* DDR3-1333G DDR3-1333H DDR3-1333J* |
166⅔ | 6 | 666⅔ | 1333⅓ | PC3-10600 | 10666⅔ | 7-7-7 8-8-8 9-9-9 10-10-10 |
10 12 13 15 |
| DDR3-1600G* DDR3-1600H DDR3-1600J DDR3-1600K |
200 | 5 | 800 | 1600 | PC3-12800 | 12800 | 8-8-8 9-9-9 10-10-10 11-11-11 12-12-12 |
10 11 12 13 |
| DDR3-1866J* DDR3-1866K DDR3-1866L DDR3-1866M* |
233⅓ | 4 | 933⅓ | 1866⅔ | PC3-14900 | 14933⅓ | 10-10-10 11-11-11 12-12-12 13-13-13 |
10 11 12 13 |
| DDR3-2133K* DDR3-2133L DDR3-2133M DDR3-2133N* |
266⅔ | 3 | 1066⅔ | 2133⅓ | PC3-17000 | 17066⅔ | 11-11-11 12-12-12 13-13-13 14-14-14 |
10 11 12 13 |
In addition to bandwidth and capacity variants, DDR3 modules can optionally implement:
- ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC3-10600 ECC or PC3-10600E is a PC3-10600 module with ECC.
- Be "registered" ("buffered"), which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, e.g. PC3-10600R. Typically modules with this designation are actually ECC Registered, but the 'E' of 'ECC' is not always shown. Whereas non-registered (a.k.a. unbuffered RAM) may be identified by an additional U in the designation. e.g. PC3-10600U.
- Be fully buffered modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.
- Be Load reduced modules, which are designated by LR and are similar to registered/buffered memory, in a way that LRDIMM modules buffer both control and data lines while retaining the parallel nature of all signals. As such, LRDIMM memory provides large overall maximum memory capacities, while addressing some of the performance and power consumption issues of FB memory induced by the required conversion between serial and parallel signal forms.
Both FBDIMM (fully buffered) and LRDIMM (load reduced) memory types are designed primarily to control the amount of electric current flowing to and from the memory chips at any given time. They are not compatible with registered/buffered memory, and motherboards that require them usually will not accept any other kind of memory.
DDR4 SDRAM
The latest generation of memory technology, DDR4, was released to the market in 2014. Compared to DDR3 memory, DDR4 memory uses 30% less power with a typical supply voltage of just 1.2V with low-voltage 1.05V modules still to come. DDR4 allows for much higher 64GB modules (compared to a maximum of 16GB with DDR3) and can also transfer data at rates up to 25.6 GB per second.
DDR4 DIMMs have 288 pins and are electrically incompatible with DDR3. The two are prevented from being accidentally interchanged by different key notch positions on the DIMMs. DDR4 SO-DIMMs have 260 pins.
Like DDR2 and DDR3 before them, DDR4 DIMMs are identified by their peak transfer capacity (often called bandwidth). The JEDEC standards for DDR3 memory are listed below:
288-pin DDR4 DIMM's
260-pin DDR4 SO-DIMM's
| Standard name
|
Memory clock
(MHz) |
I/O bus clock
(MHz) |
Data rate
(MT/s) |
Module name
|
Peak transfer rate
(MB/s) |
Timings
(CL-tRCD-tRP) |
CAS latency
(ns) |
|---|---|---|---|---|---|---|---|
|
DDR4-1600J* |
200 | 800 | 1600 | PC4-12800 | 12800 |
10-10-10 |
12.5 13.75 15 |
| DDR4-1866L* DDR4-1866M DDR4-1866N |
233⅓ | 933⅓ | 1866⅔ | PC4-14900 | 14933⅓ | 12-12-12 13-13-13 14-14-14 |
12.857 13.929 15 |
| DDR4-2133N* DDR4-2133P DDR4-2133R |
266⅓ | 1066⅔ | 2133⅓ | PC4-17000 | 17066⅔ | 14-14-14 15-15-15 16-16-16 |
13.125 14.063 15 |
|
DDR4-2400P* |
300 | 1200 | 2400 | PC4-19200 | 19200 | 15-15-15 16-16-16 17-17-17 18-18-18 |
12.5 13.32 14.16 15 |
|
DDR4-2666T* |
325 | 1333 | 2666 | PC4-21333 | 21333 | 17-17-17 18-18-18 19-19-19 20-20-20 |
12.75 13.5 14.25 15 |
|
DDR4-2933V |
366.6 | 1466.5 | 2933 | PC4-23466 | 23466 | 19-19-19 20-20-20 21-21-21 22-22-22 |
12.96 13.64 14.32 15 |
|
DDR4-3200W |
400 | 1600 | 3200 | PC4-25600 | 25600 | 20-20-20 22-22-22 24-24-24 |
12.5 13.75 15 |
In addition to bandwidth and capacity variants, DDR4 modules can optionally implement:
- ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC4-19200 ECC or PC4-19200E is a PC4-19200 module with ECC.
- Be "registered" ("buffered"), which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, e.g. PC4-19200R. Typically modules with this designation are actually ECC Registered, but the 'E' of 'ECC' is not always shown. Whereas non-registered (a.k.a. unbuffered RAM) may be identified by an additional U in the designation. e.g. PC4-19200U.
- Be Load reduced modules, which are designated by LR and are similar to registered/buffered memory, in a way that LRDIMM modules buffer both control and data lines while retaining the parallel nature of all signals. As such, LRDIMM memory provides larger overall maximum memory capacities, while addressing some of the performance and power consumption issues of FB memory induced by the required conversion between serial and parallel signal forms.
Both FBDIMM (fully buffered) and LRDIMM (load reduced) memory types are designed primarily to control the amount of electric current flowing to and from the memory chips at any given time. They are not compatible with registered/buffered memory, and motherboards that require them usually will not accept any other kind of memory.
This document includes material from the articles DDR3_SDRAM and DDR4_SDRAM on wikipedia.
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